Specification Document
PCB File Management
Abstract:
This document establishes a system for managing PCB designs. It describes templates, file locations, and a numbering scheme to establish continuity. It also provides instructions for designing in OrCAD or EAGLE and using the Electronics Shop’s board maker.
Document Revision History
The purpose of this document is to ensure that boards survive beyond the specific project they were created for. They should survive the graduation of a student or turnover among the faculty and staff.
This document applies to boards designed by students, faculty, and staff of the Power and Energy Systems Area at UIUC, primarily associated with the Grainger CEME. Additionally, it applies to boards designed by other layout technicians, either within the department or contract, which involve the Grainger CEME. Additionally, it applies to breadboards that contain important circuit designs that should be re-creatable.
IC designs are similar to board layouts, but different. A separate archive system will be created for them.
All boards which become part of the instructional lab in 50EL must be documented. This applies to wire-wrap boards, boards fabricated by the electronics shop, and boards fabricated by a commercial PCB fabricator.
Schematic: The electrical design of the board.
Layout: The physical design of the board.
Gerbers: The output from the layout tool that is given to the board fabrication shop. Typically a zip file containing one or two files per layer.
In addition, the Electronics Shop can make some boards. They recommend using EasyTrax, available at
http://www.ece.uiuc.edu/eshop/pcbdesign/. See sections 4.5 and 5.3 for information on making Layout Plus generate the same information.
EAGLE and OrCAD have both been around for over a decade. OrCAD grew through acquisition and added PSpice around version 8 (ca. 2001). Later, OrCAD was acquired by Cadence. Cadence has another layout package, Allegro, which is powerful but has an extremely steep learning curve. The ECE department purchases annual licenses for the whole Cadence suite primarily for classroom uses of PSpice.
Cadence is slowly phasing OrCAD products out. They no longer sell Capture or Layout directly, only through EMA, a value-added reseller. Each new release is a little bit worse and slightly broken. For example, designers may no longer re-number components in Layout and properly back-annotate to Capture. The linkage gets broken and cannot be easily fixed.
SmartSpark Energy Systems, a start-up company co-founded by Prof. Krein, Prof. Chapman, and Jonathan Kimball, uses EAGLE. EAGLE is much less expensive than OrCAD overall. It does not include some of the features of the OrCAD family, but at the same time, EAGLE is much less broken. EAGLE is the primary product of CadSoft Computer Gmbh, distributed in the
US by CadSoft
USA (
www.cadsoftusa.com). Regular release of new updates shows that CadSoft is committed to the product. EAGLE is available for Windows, Linux, and Macintosh operating systems.
PCB designers in the Grainger CEME may use either OrCAD or EAGLE, depending on the application. As Prof. Krein pointed out, purchasing EAGLE doesn’t mean that we lose anything that OrCAD has, it just adds another tool that researchers may choose to use.
The OrCAD suite is composed of three elements: Capture, Layout, and PSpice. PSpice processes Capture schematics into appropriate text files for simulation. PSpice users should continue to use OrCAD. Capture is used to draw schematics. Layout is used to design the physical printed circuit boards. A typical design flow is to (1) draw a block diagram in Capture, (2) draw schematics for each block in Capture, (3) assign footprints to every part, (4) create a netlist, (5) import the netlist into Layout, and (6) design the PCB. Typically, designers must cycle around steps 4-6 with back-annotation from Layout to Capture in the event of changes to the circuit.
EAGLE is an integrated development environment. Schematics and layouts are kept in separate files, but they both have the same name and are in the same folder. A change in one immediately shows up in the other. While it is possible to become unsynchronized, a designer has to make an effort to do so. EAGLE libraries each contain schematic symbols, footprints, and “parts” that are used to link symbols to footprints. Designers must choose a footprint as they place each part in the schematic. Of course the footprint can be changed later, but this forces you to think about layout at all times. EAGLE does not support hierarchical design. Since CadSoft is German, many of the parts are designed in metric units, e.g., 10 mm instead of 0.4”. EAGLE also makes use of a command line.
Each schematic is assigned a number for reference. The first schematic is SK0000. Schematic revisions are numbered, starting at rev 1. The complete filename should be SK0000_1.*. A list of schematics is kept in an Excel spreadsheet at
\\Ece-powernts2\ECE Power Design Archives\PCBs\catalog.xls. The catalog serves as a cross-reference between schematic numbers and their actual contents, including which larger project they are a part of. It is possible, even probable, that there will be several schematic base numbers that correspond to similar schematics. However, it is advisable to start on a new number whenever there are significant changes in circuitry, additional functionality, different applications, etc.
To keep within an 8-character filename, only 9 revisions are possible (1 through 9). For this reason, official revisions should be somewhat limited. A good rule of thumb is that a schematic should be revised officially whenever something significant happens:
· Fabrication of the board
· Move from breadboard to layout
· Graduation of a student
· Termination of a project
Don’t be afraid, though, of moving to a 9-character filename if you need to revise something that is at rev 9. You may ask yourself whether you are still really working on the same schematic as you were at rev 1.
Each schematic should be kept in its own folder at \\Ece-powernts2\ECE Power Design Archives\PCBs\schematics\sk0000_1 (for example, note underscore character). Within this folder, include the following at a minimum:
· A single Capture .opj file
· A single Capture .dsn file
· Bill of materials in Excel spreadsheet, at a minimum listing reference designators vs. manufacturer part numbers or values
· Data sheets on new components
· Capture .olb file with new components
· Revision description text file
· A PDF of the layout (EXTREMELY IMPORTANT)
Confusion should be kept to a minimum by only having one of each kind of file. That way, there is no misunderstanding about which is the real schematic or library or …. If you would like to keep copies along the way, make a subfolder and put them there. Additionally, the schematic title block should contain the schematic number and revision.
It is also a good idea to write a design document for major boards. This would include information that is not obvious (such as how to re-calculate values for a different application) to the average grad student or faculty/staff. It would also include known problems discovered after release. It may be tied in with the layout as well. It may reference a report, paper, or thesis.
A text document should be located in the schematic folder with either a reference to the design document or a brief description of the same kinds of information. The text document may also contain other references, such as related schematics. It should also contain a brief rev description, such as, “Adapted from SK0123_2 with change in main supply voltage,” or “Changed control loop architecture from current-mode to SCM.” It must also contain contact information for the designer (name and email address at a minimum).
Prior to release, all of this information should reside on the engineer’s computer in a distinct folder. The release process should mostly involve copying the folder onto the server.
If the schematic is going to be shared outside of the department, it should be converted to some universally viewable format. A good example is Acrobat PDF format.
All layouts receive a number similar to the schematic, PB0000. Revisions are lettered starting at A, for a complete filename PB0000_A.*. Again, all layouts are cataloged in
\\Ece-powernts2\ECE Power Design Archives\PCBs\catalog.xls. Additionally, this catalog lists which schematic number and revision was used to generate the layout. All layouts must have an associated schematic.
It is possible to revise the schematic and layout separately, so their rev codes may not match. This is OK. However, whenever revising a layout, be sure to use the most current schematic. Release layout revisions whenever major events happen, as with schematics.
· One Layout .max file
· One Layout .min file (a text format that might be useful for assembly)
· The .mnl file from which the layout was generated
· Revision information text file
· Layout .llb file with new parts
· Datasheets on new parts
· Gerber .zip file
The revision information text file is similar in purpose to the schematic revision text file. Again it should contain either a reference to a design document (perhaps the same one as the schematic) or a brief version of it, plus a brief rev description like, “Updated to SK0213_3 changes” or “Corrected footprint on U2”.
If the board is going to be stuffed by someone other than the designer, and there are specific things the assembler needs to know, it is a good idea to generate an assembly drawing. This might specify locations of heat sinks, etc.
In the layout itself, the board must be documented. That way, someone who picks up the board can figure out what it is years later. Include, at a minimum:
· Board number (PB0000)
· Revision (Rev A)
If space allows, also include:
· Board title (Battery Equalizer)
· Designer’s Name (Rob Balog)
· Copyright UIUC with the year (UIUC © 2003)
· “Stuffed on [ ]” where “[ ]” is a solid block of silkscreen for marking on
Ideally, all of this information should be in silkscreen. If this is not possible, it can be put in copper on the solder side of the board.
The gerber file should be a zip file that contains the following:
· Artwork in RS-274D or RS-274X format for each layer of copper
· Artwork in the same format for the soldermask and silkscreen
· Excellon drill file and tool list
· Fabrication document listing which file corresponds to which layer, what the copper weight is, dimensional information, tool list, and other information important to the vendor
When in doubt, consult with the supplier (currently Advanced Circuits) for what they need. Technically, for prototypes, a fabrication drawing is not necessary if you plan to accept standard rules. If the board is special in any way (different copper weight, routed outlines or holes, etc.), and it is going to be built more than once, it is good practice to include a fab drawing.
The Electronics Shop has the capability to manufacture some boards. Depending on the design, this can be a very inexpensive way to fabricate one-off boards. Some things to keep in mind:
· Jim Wehmer claims he can achieve 10 mil line/space. However, he said that the wider the tracks and the bigger the spaces, the better. The author recommends 25 mil rules with the largest annular ring possible. PB0004 rev A was designed with 15 mil rules and 12 mil annular rings. The board is usable as fabricated, but the traces are actually closer to 25 mils, and some of the holes barely hit the pads.
· The boards manufactured are 1 oz. 2-layer with no plated through-holes, no solder mask, no silkscreen. The author has not investigated heavier copper.
· If Jim needs to spend a lot of time on the project, such as interpreting files in the wrong format, the costs easily spiral out of control at $35/hr.
The software the shop uses relies on manually entering apertures and drill tools. See the next section for aperture information. Keep the drill tool list to a minimum. As of this writing, there is no way to force OrCAD to use a specific tool list. So, Jim will have to manually enter each tool.
Generate top, bottom, and cut-out RS-274D files (2.3 format) as *.GTL, *.GBL, and *.GM2. The cut-out layer should just be the board outline, and any internal cut-outs required. Jim will also need THRUHOLE.TAP (Excellon drill file) and *.DTS (drill tool list).
For Capture, before creating a new schematic, first populate the information in Options -> Design Template -> Title Block. This will automatically populate some minimum information in the new schematic. As you create new pages, be sure to update the information.
For Layout, use sizea.tpl in
\\Ece-powernts2\ECE Power Design Archives\PCBs\lib\. If your design is too big to fit comfortably on size A paper, use instead the templates bc.tpl, cc.tpl, or dc.tpl in …\Layout_Plus\data. Be sure to check the layer information, route spacing, etc.
There are (or will be) libraries at
\\Ece-powernts2\ECE Power Design Archives\PCBs\lib\ for both Capture and Layout. When working on a design, put all new parts in new libraries. Periodically, someone (probably the author) will review all of the new libraries and move relevant parts into the central libraries. When starting a new design, check the central libraries first, then related libraries from similar projects that are more recent than the central libraries, then create a new library if necessary. Until we have done several designs, many parts will be new.
Also, Cadence supplies some libraries. Use them, but double-check them. If you find a problem, save the modified symbol/footprint as a new name in your new library. For this reason, always check the central libraries first because someone may have found and fixed a problem in the Cadence libraries.
There are a couple of key items to consider if you plan to have the Electronics Shop fabricate your board.
1. Apertures are entered manually. Do not allow OrCAD to automatically add apertures. Instead, if you are using sizea.tpl (after 3/24/2003), select, “Use Existing Apertures Only” under Gerber Preferences. If you are using some other template, or the board is historical and you want to revive it, select, “Using Master Aperture List.” The master aperture list is in the library directory, easytrax.app. If for some reason this aperture list is inadequate for your design, add more apertures starting with D34 (skip 33). Then be sure to tell Jim about it, and export your aperture list for him to use as reference.
2. Drill tools are entered manually. The author has found no work-around for this. The best solution is to use a minimal number of drill tools. The tool sizes available are:
mm
|
3.0
|
2.5
|
2.0
|
1.5
|
1.1
|
0.8
|
0.7
|
0.6
|
0.5
|
mils
|
120
|
100
|
080
|
060
|
045
|
032
|
028
|
024
|
020
|
You MUST design for these tool sizes. The alternative is a finished board with holes that are too small for the part. Your tool list should give the metric dimension.
3. You must generate exactly the files necessary, just as if you were using EasyTrax. The necessary files are *.gtl (top), *.gbl (bottom), and *.gm2 (cut-out). You must use RS-274D, 2.3 format. THRUHOLE.TAP must be modified by removing one zero from each X and Y coordinate (making the entries in mils, not 0.1 mils). You must also provide *.dts as a list of the drill tools in mm.
4. The board will be fabricated with no silkscreen. Remember that you will need to stuff the board, and make proper allowances in the design so you will know where parts go. For example, turn off the silkscreen and make sure you can see where everything goes.
5. The board will be fabricated with no plating. Remember to solder in wires at every via to make the top-to-bottom connection. For this reason, consider minimizing the number of vias.
6. The cut-out layer can contain simply the board outline, or complicated shapes inside the board. The recommended procedure is to use a 100 mil line to draw the “board outline”, then a 10 mil line on ASSY BOT that will be processed as *.gm2. The 100 mil line represents the actual width of the cutting tool.
7. The cost structure is based on material cost and milling time, both of which point towards “smaller is cheaper”, plus technician time. For most boards, technician time will dominate. Keep this to a minimum by providing files in the proper formats with the proper names, restricting to the given apertures, and minimizing drill tools. PB0004 rev A was manufactured by the Electronics Shop for $52.50.
8. The software involved is DOS based, so keep to 8-character file names.
EAGLE is a unified design environment. Designers cannot readily separate schematic design from board layout. A new data management paradigm is used instead. For a personal computer, the default location for project data is C:\Program Files\EAGLE-4.16\projects (for version 4.16).
IMPORTANT: EAGLE defaults to putting projects in the EAGLE directory. This is not appropriate in 327 EL, since the computers are regularly wiped and re-installed. When you first start EAGLE, in the Control Panel window, go to Options → Directories…. Change the “Projects” directory to “H:\EAGLE.” This will create a directory on your personal folder on the server. That way your files are always accessible from lab computers. People who have EAGLE installed on personal machines might also want to specify a different project directory, such as “C:\Documents and Settings\username\My Documents\EAGLE.” That simplifies back-ups and other computer administration tasks.
The first step in creating a design is to update the Excel spreadsheet. EAGLE designs are numbered PCB5xxxx. Note the different prefix and that numbering starts at 50000. In the spreadsheet, enter a new line for a new design.
Start EAGLE. Create a folder named, for example, PCB54321 (or whatever your board number is). Within the folder, create a new project named Rev A. Right-click on the project and create a new schematic. Save it as, for example, pcb54321_a1.sch. As you go through the design, save frequently; occasionally, save as a new number (e.g. pcb54321_a2.sch). Before drawing any of the schematic, place LETTER_L at the origin, which gives you a good frame for landscape-oriented letter-size paper. You may need to go in the EAGLE Control Panel, right-click on “Libraries,” and select “Use all.”
When you are essentially done with the schematic, click the “Switch to Board” button. This will automatically create a new layout with the same name as the schematic but .brd suffix. As you go through, again occasionally save it as a new number. Doing a “Save As” in either schematic or layout windows will automatically save the other file simultaneously with synchronized file names.
When you are completely done, do a “Save As” and name the file e.g. pcb54321_a.sch or .brd. This will mark the final version as the un-numbered file. Create PDFs of the schematic and layout and put them in the Rev A folder. Create gerbers and put them in a subfolder and a zip file. Copy the whole folder over to the appropriate folder on
\\ece-powernts2\ECE Power Design Archives\PCBs\EAGLE Designs\.
Revising a design is similar to creating one. First, enter the new revision in the spreadsheet. Next, make sure you have the old revision in a folder in your projects directory. The example is making revision B of PCB54321.
So revision A is a project in PCB54321\Rev A. Right-click on the PCB54321 folder and create a new project, named “Rev B.” Click and drag pcb54321_a.sch to Rev B while holding down the control key to make a copy. Do the same with pcb54321_a.brd. Open pcb54321_a.sch (the one that is in your new Rev B project). Do a “Save As” to pcb54321_b1.sch. Everything should now be properly synchronized so that you can proceed with changing the schematic and/or layout.
Again, once you are done, do a “save as” and create PDFs and gerbers. Put the whole folder in the archives.
Libraries in EAGLE contain three entities: packages, symbols, and parts. A “package” is what most people call a footprint. It goes in the layout and has the pads, holes, silkscreen, etc. that go on the actual board. A “symbol” is what you see in the schematic. It may represent a whole device or some part of one (such as one gate of a quad NAND). A “part” ties it all together. A part may be composed of several gates, each with their own symbol, and has one or more packages. You must tie pins from gates to pins on the package as well as defining the default prefix for the part.
As much as possible, symbols and packages should be generic. Parts can be as specific as necessary.
When creating packages, choose a round number of mils for the drill size. EAGLE is naturally metric—for example, the default is 0.8mm rather than 0.032” (32 mils). You must type in the hole size you desire.
In OrCAD Layout, library parts have padstacks that define the pad sizes for each layer. In EAGLE, this is handled within the board design itself with the “restring” settings. The default settings are fine. That means that you don’t need to worry about pad sizes within the library, only the drill size. EAGLE derives the pads from the holes.
6.4 Creating Gerbers
Before you create the gerber files for fabrication, do the following:
· Add PCBxxxxx REV x in copper on either the top or the bottom.
· Add PCBxxxxx REV x, your name, and a copyright notice in the top silkscreen.
· Go to Options->Set->Drill. Click “Set.” This calculates all the active drill sizes and assigns symbols.
Then go to File->CAM Processor, then File->Open->Job…. Open “make_output.cam,” which is located in
\\ece-powernts2\ECE Power Design Archives\PCBs\lib\EAGLE\. Edit if necessary, such as adding outputs for a four-layer board. The outputs will all be in your “Rev A” (for example) folder. Create a “gerber” subfolder and move the gerber files into it. Also, copy
\\ece-powernts2\ECE Power Design Archives\PCBs\lib\EAGLE\readme.txt into the gerber folder and modify it appropriately. You may need to delete some extra files, such as assembly drawings and bottom side silkscreen. Make sure the readme.txt lines up with the actual files.
The following list appears in the EasyTrax readme file.
AWG
|
Mils Dia
|
|
AWG
|
Mils Dia
|
0
|
325
|
|
18
|
040
|
1
|
289
|
|
19
|
036
|
2
|
258
|
|
20
|
032
|
3
|
229
|
|
21
|
028
|
4
|
204
|
|
22
|
025
|
5
|
182
|
|
23
|
023
|
6
|
162
|
|
24
|
020
|
7
|
144
|
|
25
|
018
|
8
|
128
|
|
26
|
016
|
9
|
114
|
|
27
|
014
|
10
|
102
|
|
28
|
013
|
11
|
091
|
|
29
|
011
|
12
|
081
|
|
30
|
010
|
13
|
072
|
|
31
|
009
|
14
|
064
|
|
32
|
008
|
15
|
057
|
|
33
|
007.1
|
16
|
051
|
|
34
|
006.3
|
17
|
045
|
|
35
|
005.6
|
The following rules were obtained from Circuit Science, a PCB fabricator in Minneapolis. These rules maximize the manufacturability of the board. Generally, it is possible to demand smaller lines and spaces, but at increased cost. According to Allen Bennink of OEM Engineering Services, the hole size should be 8 mils larger than the max dimension of the pin to get good wicking of the solder into the hole. For example, a 25 mil square pin calls for a 43 or 44 mil hole.
Copper Weight (oz/in2)
|
1
|
2
|
3
|
4
|
(Pad size) - (hole size), diameter
|
20
|
20
|
20
|
20
|
Finished hole to hole space, from outer edges
|
25
|
28
|
30
|
32
|
Feature to feature space
|
5
|
8
|
10
|
12
|
(Thermal ID) - (hole size)
|
20
|
20
|
20
|
20
|
(Thermal OD) - (Thermal ID)
|
8
|
10
|
14
|
16
|
(Plane clearance) - (hole size) (remove unused pads)
|
13.5
|
16
|
17
|
18
|
Plane to plane space
|
9
|
10
|
14
|
16
|
Minimum line width
|
5
|
8
|
12
|
20
|
Minimum finished hole size
|
5
|
9.5
|
20
|
30
|
Etch compensation applied by manufacturer
|
1
|
2
|
4
|
6
|
